As many of you recall from our post on December 24th, 2025, we hit a significant roadblock with our hardware testing. During the last shipment of one of the DevKits at our disposal, the power supply (which we had already replaced) and the T2080 motherboard sustained damage.
Since then, we have spent quite a few hours on the workbench trying to revive the NXP T2080RDB DevKit, but the situation remains critical.
A photo of the NXP T2080RDB reference DevKit board.
The symptoms
The behavior is consistent but frustrating. We hooked up the serial console, hoping for some life, but unfortunately, no information came out of the serial port. It is complete silence.
As soon as we power up the board, a specific LED close to the CPU turns on. After checking the technical documentation, this indicator seems to signal that the CPU is being kept in a sleep state.
The investigation
So far, none of our attempts have led to a breakthrough or even a solid theory, so we are currently clueless.
To dig deeper, we had to get creative with our quite limited diagnostic tools. We decided to investigate the electronic components and connections on the DevKit board using a piece of classic equipment we had on hand: a very old Tektronix T935A oscilloscope.
Photograph showing a flat signal in the oscilloscope connected to components of the T2080RDB devkit.
For those interested in vintage test gear, the Tektronix T935 is a 35 MHz dual-channel analog scope with a delayed timebase from the T900 series. The specific model we are using, the T935A, is an upgraded version of the standard T935 (and the single-timebase T932).
The “A-series” adds some very useful features that came in handy during our probing:
Differential input (A-B)
X/Y mode in full sensitivity for both channels
DC trigger coupling and composite trigger
User-selectable CHOP/ALT mode (Non-A series select this automatically based on sweep rate)
We painstakingly probed the board using the T935A. Although it cannot detect the high-frequency bus operation of the CPU or DDR lines, many components can be seen. High-impedance readings allow us to check the pins, and we can verify the power lines.
Beyond signal probing, we also attempted to force the board to boot from different media. We altered the DIP switches to try booting from the SD card, the NAND flash, and the SPI flash. The oscilloscope should show us chip selects of them to show read activity.
We tested the electric signals associated with:
The main power lines (fine)
The SD card interface (no activity)
The NOR and NAND flash interfaces (no activity)
The oscillators that provide clock sources for CPU and RAM (fine: 66 MHz and 133 MHz)
The reset lines of the T2080 CPU (one good, one shows no activity)
The CPU clock input line (dead?)
Photograph taken during the electrical track testing session of some components of the T2080RDB devkit.
Current status and next steps
Unfortunately, even with a detailed signal analysis and configuration changes, the CPU remains stuck in reset. The CPLD attempts to pull the CPU out of reset; however, the clock input is dead, and the HRESET line stays low.
The boot phase fails very early. Perhaps the CPLD did not complete the sequence, or maybe it is corrupted. There may also be a hardware issue. A visual inspection shows nothing apparent; we removed the CPU heatsink. The CPU remains cool, which proves that it is not running.
If anyone has experience with T2080RDB boards getting stuck in a reset state or has suggestions on what to probe next, please reach out!
Today we publish here ( above) an export from PCB design of our PowerPC Desktop motherboard (based on processor NXP T2080) , you can see the motherboard top view with components and connectors, it reflect the progress on pcb design, that is going fast. Before the end of January will be completed !! In January should be defined the costs and timing for the production of the prototypes.
The dispositions of components on the board are not final.
As requested by our association members there are 4 holes 30-42-60-80 for the left M.2 connector.
The two Ethernet are one on top of the other.
There is even a digital audio output.
There are 3 PCIE connectors: 16x, 4x Open ( with space for 8x and 16x), 1x
In the mean time that is in progress the donation campaign for the schematics design we open now the donation campaign for the PCB design.
PCB Design of Desktop Powerboard Tyche
Starting from the source of the Electronic Schematics design design the PCB means prepare all physical PCB layers lanes and components disposition and connection to go in production with prototypes.
Designer have take from NXP Devkit design ( 2023 version) everything is related to boot process and many parts from our Notebook design, except what is not needed for Dekstop version, like the Battery part.
SPECS
Form Factor: Micro ATX
CPU: NXP T2080, e6500 64-bit Power Architecture with Altivec technology
4 x e6500 dual-threaded cores, low-latency backside 2MB L2 cache, 16GFLOPS x core
RAM: 2 x DDR3 slots
VIDEO
PCIE3 x16 VIDEO Card 1PCIE2 x4 VIDEO Card 2
AUDIO: C-Media 8828 sound chip, audio IN and audio OUT jacks
USB: 3.0 and 2.0 ports
STORAGE:
NVM Express (NVMe)M.2 2280 connector2 x SATA21 x SDHC card reader
The timing of milestone depend from your donation. Thanks!
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Payment Methods
Online Donation – PayPal
Press Donate and as Payment Method select PayPal You can choose one time donations, or recurring -smaller- monthly donations ( and with others selected frequency). ( How stop paypal recurring payment )
Online Donation – Stripe
Press Donate and as Payment Method select Stripe You can choose one time donations, or recurring -smaller- monthly donations ( and with others selected frequency).
Offline Donation – Bank credit transfer
These are the bank account details for donating:
Bank name: Banca Popolare Etica
Bank account owner: Power Progress Community OdV
IBAN: IT94X0501801600000012339610
Beneficiary Bank (57)
Code BIC/ SWIFT: ETICIT22XXX
Banca popolare Etica SCPA Via N. Tommaseo 7, 35131 Padova (PD)
Intermediary Bank (56A)
Code BIC/ SWIFT: POSOIT22XXX
Banca popolare di Sondrio
Piazza Garibaldi 16, 23100 Sondrio (SO)
CAUSE:“PPC notebook donation – NAME and SURNAME”
Where the NAME and SURNAME are the same you will fill in the Donate page.
After you have made the bank transfer press Donate and as Payment Method select Offline Donation.
In Offline donation the recurring donations is only a declaration of intent as the system doesn’t do anything for you.
Anonymous Donations
When you make the donation (offline or online) you can choose to make your donation anonymous.
Preferred payment method and TransferWise / CurrencyFair
Our preferred payment method to receive donations (to keep commission and also your costs low) would be:
EU donors: Bank Transfer (online or offline)Non-EU donors: Bank Transfer with services like Wise or CurrencyFair
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Donations are liberal and not refundable
The Power Progress Community is a nonprofit organization established in Italy. The Italian law allow to collect liberal and not refundable donations meant to pursue the missions and projects of the association and not give back products.
Restrictions for a nonprofit associations in Italy
An organization like ours has to take into account the following constraints:
A nonprofit association cannot make commercial products;The association can receive donations, but cannot refund them;The association must be coherent with its mission, and is allowed to ask for donations for their achieving the goals.
So, what we can do to start our project is based on the points below:
The association can have a particular goal to reach and ask donation to achieve it, but it cannot give back the money (no refunds).Donation must be altruist so, no one will receive something back for their donation.Italian law allows an association to finance an R&D for a project or activity.
What happens if the campaign fails?
As stated above, we will not be able to refund the donors in any case. Because of that, if the money collected is not enough to fund this research we will use it for another goal within the mission of the organization.
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Will all the received money be used for the research?
Almost, as any payment platform available, either PayPal, Stripe or the Bank account transfers, have a fee applied to each donation. As non-profit organization we have inside EU 1,8%+0,35euro of commission, outside EU 2,8%+0,35 euro ( from some country we see that could arrive to 4% of commission) for paypal. In case your bank transfer is from outside EU, for us bank commission cost is high: 6 euro, so we strongly suggest to use service like Transferwise to decrease the commission cost for both.
Open Hardware Certificaion
As a final remark, we will try to adhere to the Open Source Hardware requirements in the design of this laptop motherboard, therefore we are strongly committed in avoiding any hardware component requiring an NDA (Not Disclosure Agreement).
For this purpose, we have contacted many chips vendors in order to verify their agreement to distribute as Open Source Hardware our electrical schematics and PCB design obtained in this second campaign.
Among others, NXP which is the company producing the selected CPU, has answered positively for the Powerboard Tyche Notebook that had taken from T2080RDB Revision C design, now we are waiting the level and parts that they agreed for T2080RDB Revision F, that’s the new version that we have use for the new design of Powerboard Tyche Desktop,
The process required to achieve a fully compliant Open Hardware motherboard, was carefully analyzed by students of the Law and Policy Clinic of New York University School of Law. Thanks to their work, are clear the practical implications of the requirements for the OSWHA Open Hardware certification, and cross-checked our approach and adopted solutions with OSWHA personnel.
An important part of being considered Open Hardware compliant (OSHWA Open Hardware certification), require that everything that is under our control and that is used to produce our motherboard, should be publicly disclosed, such as schematics, PCB, Gerber-files and all their accompanying information.
As a consequence, most of the datasheets of the chips used in our schematics are freely downloadable, as well as the schematics and the PCB design.
In case some of the chip vendors will ask us to remove technical details that we were not supposed to disclose, we will comply to their requests by removing the published material, but that will do not impact on our compliance to OSHWA Open Hardware certification because we could demonstrate that we strived to be as open as we could.
We are sure that you will be satisfied by the final PCB design, and you will be proud of being one of the contributors that could make materialize the first and only Open Hardware complaint PowerPC desktop motherboard designed around GNU/Linux!!
Payments we should do next days:
Schematics Design
Before 31 December we should balance the payment for the schematics design plus 850 euro needed to fill the review questionnaire asked by NXP, So we have summed the 850 euro to the running campaign for the Schematics.
54.42% Raised
€3,401.56 donated of €6,250.00 goal
32 Donors
48 Days Left
PCB Design
We need to pay at beginning of January the 50% of the cost for PCB design that is around 6100 euro, so we have created the PCB design campaign that is 12500 euro ( 10000+VAT+paypal/stripe fees) .
We thanks donors and collaborators that permit us to finance everything realized until now.
We are going faster as promised, to realize a working Open Hardware PowerPC motherboard in few months , that increase rhythms of design and production, costs and ask us to increase even the rhythm of donations…
Donation is a form of collaboration so apart your one shot or recurrent donation that are welcome, we even ask you to spread all over you can our project so more potential collaborators could join our project.
On 12th December NXP confirm us that the review of our source schematics was submitted, they don’t give us any estimation on how much time they take to do the revision and to give us the permission to publish as Open Hardware the schematics source. After we will have the agreement from NXP we will publish the sources as we do usually, as we have done for our Powerboard Tyche Notebook motherboard sources.
Debian 13 installer for PPC64 and powerpc (32bit)
We are very happy that Debian ports team have published a working Debian 13 installer for PPC64 and powerpc so we have tested on PowerBook G4 and IMac G5. Please join us if you want to help on test Debian PPC64 package or if you want to test even Mint PPC
During the last shipment of one of the Devkit at our disposal, the power supply (already replaced) and the T2080 motherboard were damaged, so we are currently unable to test Debian 13 on it.
Our Devkit T2080 RDB board
If you want to install Debian ppc64/ppc32 on your G5 or G4 you could appreciate our wiki page updated from our collaborators Debian PowerPC Wiki
We now have the complete electronic source design for our new desktop design in our hands!
This week, ACube Systems and some volunteers from our association will review the design. We expect the manufacturer to start setting up the PCB layout for the new Powerboard Tyche Desktop on October 20th. This is part of our strategy to focus on creating a stable, functional desktop version of the core computing platform by the end of 2025.
The PCB design phase (Phase 2) will begin shortly after the schematics and Bill of Materials (BOM) are sent to the manufacturer. We anticipate that this step will allow the manufacturer to provide us with an estimate of the cost and timeline for the PCB layout design. This cost and timing estimate will then be shared with the community “just in time.”
Technical Components and NXP Review
We have verified that the availability of SATA2/3 controllers is poor, and the chip Lattice Silicon Image SiI3132 chip that we selected is no exception. We decided to include it in our desktop board to ensure backward compatibility with SATA devices, such as DVD and HDD.
We do not use the on-chip T2080 SATA2 controller because we prefer to use the T2080’s three x4 PCIe Gen3 configuration to optimize the speed of video cards and storage controllers. This configuration cannot coexist with the on-chip SATA2. In any case, the best performance is possible thanks to our M2 motherboard interfaces.
In our board design, we have an SPI connection for an external LCD, which can be used as a secondary screen or for debugging and diagnostics. It is also useful when setting up u-boot and when no video card is connected to the board.
Our board design includes GPIO connectors that can be used to connect other devices that don’t use USB, SPI, or PCIe buses.
Our desktop design is derived from our old notebook design and the original NXP T2080 RDB (Release F) design. We are integrating many components specified in the reference board, including critical monitoring hardware.
This includes the OnSemi ADT7481ARMZ thermal monitor, which has been upgraded to the OnSemi NCT72. The ADT7481 is used as the thermal monitor or temperature sensor on the original NXP T2080 reference design board. On that board, the ADT7481 (designated U34) is usually connected via the I2C_1 bus with the address 0x40. The T2080 processor itself contains a temperature diode designed to be used with system temperature monitoring devices, such as the Analog Devices ADT7461A. This similar part is mentioned in the documentation for the T1042 chip, which highlights the standard use of such monitoring.
Designers have changed other components from the original T2080 RDB design and our notebook design due to the availability of new compatible models, such as the N25Q512A13 FLASH SPI, which is substituted for the EvKit Micron MT25QL512A due to its limited availability.
Due to the changes in components, we will need to modify the VHDL code of the CPLD chip when we have the prototypes in our hands. Therefore, we must take into account the additional cost of this task.
To ensure full compliance and open-source publication readiness,
The designer will fill out the NXP review questionnaire [draft post 2025-10-12] simultaneously.
The questionnaire and the Cadence schematic source will then be sent to NXP.
The main goal is to receive a full or partial agreement to publish the parts of our design derived from the original NXP T2080 RDB (Release F) as open hardware.
We anticipate a robust boot-up because the components and firmware are similar to those of the stable T2080 RDB. The specific CPLD is programmed using the original CPLD source code of the T2080 RDB. Once NXP grants the necessary agreement, we plan to publish the source schematics and evaluate the use of a recent CERN Open Hardware License version.
Upcoming Project Phases
The next anticipated milestones, pending finalization of cost estimation:
Phase 2: PCB design. (tentatively scheduled two months after the completion of the schematics).
Phase 3: Prototype production (tentatively scheduled one month after PCB design).
Phase 4: Prototype testing (tentatively scheduled one month after prototype production).
We continue to rely on the community’s support. Recurring donations are dedicated to the campaign aimed at recovering costs already incurred for notebook testing and CPLD firmware fixing.
We are searching volunteers to test Debian PPC64 and fix packages
Finally, we need more volunteers to support the necessary software efforts, including Debian PPC64 testing, as we cannot ask for additional donations for this purpose.
Below is an updated list of specs for the desktop board being designed.
Form Facttor: Micro ATX
CPU: NXP T2080, e6500 64-bit Power Architecture with Altivec technology
4 x e6500 dual-threaded cores, low-latency backside 2MB L2 cache, 16GFLOPS x core
RAM: 2 x DDR3 Slots
VIDEO
PCIE3 x16 VIDEO Card 1
PCIE2 x16 VIDEO Card 2
AUDIO: C-Media 8828 sound chip, audio IN and audio OUT jacks (3x2)
USB: 2 USB 3.0 ports
2 USB 2.0 ports
2 USB 3.0 ports internal for FRONT
STORAGE:
2 NVM Express (NVMe)
2 x SATA2
1 x SDHC card reader
NETWORK:
2 x Gigabit ethernet RJ-45 connector
To complete the schematics design, the designer will need around another two weeks. From the beginning of August we already have in our hands a large part of the new design (Desktop version of Powerboard Tyche motherboard). We have started a fast review thanks to a few members of our association that were able to check the schematics. As usual in Italy, during August companies close for at least two weeks for vacations, so the designing is slowing down. For that reason, the PCB design will start after the middle of September.
We are proceeding faster than ever. We started the “Powerboard Tyche Desktop Electrical Schematics Design” donation campaign on 14th July, and the design itself started at the beginning of July. So after 1 month we already had a good part of the schematic done! Comparing that time with around 12 months that took the Notebook schematics design, now we are proceeding more than 4 times faster!!!
Thanks to the previous work done, our previous design and experience doing Powerboard Tyche Notebook designs and prototypes, the designer can realize the Desktop Design faster, integrating the NXP T2080 RDB design (revision F – year 2023). That design is possible thanks to the 5400 euro of the dedicated Donation Campaign. The old donation campaign to design the Schematics of Powerboard Tyche Notebook was 12600 euro, so now we are spending less than half.
So every past effort and past donations for the Notebook version campaigns have been invaluable and permit us to speed up time and limit the cost to design the current Desktop version.
54.42% Raised
€3,401.56 donated of €6,250.00 goal
32 Donors
48 Days Left
We remain absolutely committed to making an Open-Hardware Notebook-based PowerPC machine a reality. The desktop version will be the right step to allow more people, spending less money, to soon own, enjoy, and test software on this Desktop version. With a few changes and reintegrating the battery part of our previous Notebook, it will give rise to the Notebook version!
You can check our timeline from 2015 to 2025 and milestones of the project during the years.
NXP will review our Powerboard Tyche Desktop Electrical Schematics Design before we can publish it (completely or partially), as we have received from them Cadence source of the NXP T2080RDB (revision F – year 2023) that the designer has modified and partially integrated with our previous Notebook design (you can see our architectural study published even in the last post). We thank NXP for having provided us this source (revision F) that actually is not published. For that reason we need to have their agreement to publish, with an Open Hardware license, the parts that we take from their source. The Notebook version is published with a CERN Open Hardware license 1.2 version.
Hardware designers in NXP, as our old designer and the new one, use Cadence to design schematics, so that forces us to have the source in Cadence. We are not hardware designers. The PCB design of the Notebook board was done in Mentor Expedition and the Desktop Design will be done in Mentor Pads.
As we did with our Powerboard Tyche Notebook design, we will convert the Cadence and Mentor Pads sources to Altium and then to KiCad, hoping that the conversion to KiCad has been further improved and allows nothing to be lost.
For us, it is of fundamental importance that our board is Open Hardware (we will certify it as Open Hardware with OSHWA when it will be completely functional) and the prototypes are realized thanks to your support and donations.
The process required to achieve a fully compliant Open Hardware motherboard was carefully analyzed by students of the Law and Policy Clinic of New York University School of Law (in 2019). Thanks to their work, we clearly understood the practical implications of the requirements for the OSHWA Open Hardware certification, and we cross-checked our approach and adopted solutions with OSHWA personnel. An important part of being considered Open Hardware compliant (OSHWA Open Hardware certification) requires that everything that is under our control and used to produce our motherboard should be publicly disclosed, such as schematics, PCB, Gerber-files and all their accompanying information. As a consequence, most of the datasheets of the chips used in our schematics are freely downloadable, as well as the schematics and the PCB design. In case some of the chip vendors ask us to remove technical details that we were not supposed to disclose, we will comply with their requests by removing the published material, but that will not impact our compliance with OSHWA Open Hardware certification, because we can demonstrate that we strived to be as open as possible.
What’s more, we thank NXP for reviewing our design. We had to fill a deep questionnaire that permits them to go deeper into the review. This is an added value that NXP gives to our board: they use their time and resources for us, and we are grateful for that. In the worst case, they will ask us to mask some parts of the source that are copied from their design. That is the reason why, before publishing the schematics sources, we need to complete it and wait for their review. In this way, we have sped up the design process; we are going on with our design phases without waiting for NXP review. The review only delays the moment in which we start publishing the open source designs.
We are searching for volunteers that would like to improve our Open Hardware license and evaluate if it is better to use a newer CERN Open Hardware version than continuing with version 1.2.
What happens when the schematics design will be completed? In the middle of September we should have in our hands the schematics design and the BOM that we will forward to the company that will make for us the PCB design and prototype production. This manufacturer company is already booked and ready for the middle of September to carry out these activities for us. The first feedback that this company will give to us will be the cost estimation to design the PCB and to produce our Desktop prototypes, so at the same moment we will be able to inform everyone about the costs of each phase (PCB, prototypes).
Then they will start the PCB design (phase 2) and order the electronic components needed for the prototype production (phase 3). After the prototype production, hardware and firmware testing will start (phase 4). With the CPLD itself, starting from the original CPLD source code of T2080 RDB, our Powerboard Tyche Desktop CPLD will be programmed. As the components and firmware to boot up the board are the same as the T2080 RDB, we can count on a robust boot up. If more work is needed to improve the CPLD code, it will be done thanks to the same firmware engineer that helped us fix the CPLD firmware of our Notebook prototype, and in that case we will evaluate the cost (phase 4 bis).
Yes, it’s possible to reach the goal to have a working Powerboard Tyche Desktop before the end of 2025, but is needed an extraordinary effort from donors because we depend on donations to cover all the steps that are coming : Schematics Design, PCB Design, Prototype Production and Tests.
We are very happy to inform you that the Schematics Design of our new Powerboard Tyche Desktop is running fast thanks to the new Designer and to the NXP Devkit source design plus our Powerboard Tyche Notebook design. Designer took from the NXP Devkit design ( 2023 version) everything is related to the boot process and many parts from our Notebook design, except what is not needed for the Desktop version, like the Battery part.
You can check all the details regarding what we took from Devkit design and what we took from our Powerboard Tyche Notebook design.
At the end of July, we will provide the schematic design and the BOM to the factory, which will then begin the PCB design based on the schematics. Therefore, by the beginning of August (before the factory’s holiday closure), we will know the cost for the PCB design and prototype production. New donation campaigns will then start for PCB design and prototype production.
Today, July 14th, 2025, we’ve officially launched the donation campaign for the schematics. Before the end of July, we’ll make the down payment for the schematics design. We already have funds collected from the previous donation campaign for the CE certification (of the Powerboard Tyche Notebook), so we can advance money from that fund. However, it’s crucial to boost this new campaign and encourage everyone to donate so we can use fresh funds specifically for the schematics design.
SPECS
Form Facttor: Micro ATX
CPU: NXP T2080, e6500 64-bit Power Architecture with Altivec technology
4 x e6500 dual-threaded cores, low-latency backside 2MB L2 cache, 16GFLOPS x core
RAM: 2 x DDR3 Slots
VIDEO
PCIE3 x16 VIDEO Card 1
PCIE2 x4 VIDEO Card 2
AUDIO: C-Media 8828 sound chip, audio IN and audio OUT jacks
Yes, it’s possible to reach the goal to have a working Powerboard Tyche Desktop before the end of 2025, but is needed an extraordinary effort from donors because we depend on donations to cover all the steps that are coming : Schematics Design, PCB Design, Prototype Production and Tests.
Starting from today (July 14th 2025) you can make your donation, thanks!
Milestones
Phase 1: Actual Campaign Schematics Design : goal 30.07.2025
The milestone phases depend from your donation. Thanks!
We remain absolutely committed to making an Open-Hardware Notebook-based PowerPC machine a reality.
As we have already published on our past post we have changed the tactic, focusing on a desktop board first allows us to concentrate on getting the core computing platform stable and functional, tackling the complexities of a laptop form factor (like power management, screen integration, etc.) in a later stage if needed. This is a pragmatic step to ensure we achieve a tangible outcome by our 2025 target. What’s more the Powerboard Tyche Desktop version will be more cheaper than the Notebook version!
We value the experience of making our Open Hardware Powerboard Tyche based on PowerPC from scratch; this is possible thanks to the support of all donors and supporters, and the time and creativity of the activists who have been involved in this project over the years.
We ask you to share every-ware this call for support a strong flow of donations to cross the finish line of all donation campaigns to arrive by 2025 with produced, tested and functioning prototypes!
