This section is for people new to the PowerPC architecture (also called Power Architecture).
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The PowerPC architecture design is newer than the other successful CPU architectures:
X86 – 1978
MIPS – 1981
ARM – 1983
PowerPC – 1991
From the beginning, PowerPC was designed with more features than other CPUs.
From August 2019 Power ISA is Open, so developers can design chips based on the royalty-free instruction set. Microwatt FPGA Soft CPU Core is implemented in VHDL and released under an open source license. It will be able to run a complete linux distro soon.
Specs in short
- 64-bit architecture with a proper 32-bit subset
- Wide vector instructions with large register file allow efficient data moving without use of off-chip memory
- RISC architecture introduces Superscalar concept of multiple execution units: Branch, Fixed Integer, Floating Point
- AltiVec SIMD vector processing
- from ISA 2.04/2.05/2.06 support multicore/multithreading, virtualization, hypervisor, and Power Management (from 2007)
- Automotive – from Powertrain, Body, and Chassis, to Safety and Infotainment.
- Computing – From volume servers to the fastest and most resilient enterprise servers
- Consumer – core technology for innovative game consoles (X-Box 360, Wii, PS3)
- High Performance Computing – Sequoia, the IBM BlueGene/Q system
- Wired Communications
- Wireless Communications
Altivec Accelerator SIMD
- AltiVec technology is a vector or Single Instruction Multiple Data (SIMD) architecture that allows the simultaneous processing of floating point and integer data in parallel.
- Standard from Power ISA 2.03, developed from 1996-1998
- consists of thirty-two, 128-bit architectural registers and 16 additional vector renaming registers.
- The e6500 core includes a 16 GFLOPS AltiVec technology (adhered to Power ISA 2.0.7 – May 2013)
Specs in Depth (more info)
- Fixed-width 32-bit instructions to ease their decoding
- Load-store model, all operations are done within registers
- Large number of registers (32 general purpose registers and 32 floating point registers)
- Atomic (or exclusive) load-store instructions for use in a multicore context
- Big-endian order with the ability to work in little endian
- 64-bit architecture with the of instructions specified behaviour for this mode
- No specific role for general purpose registers (r1 used as the stack pointer is an ABI choice, not an architectural one)
- MMU model is not defined, it is implementation specific, with 2 global models for use in embedded devices or servers
Why is PowerPC Only Adopted in the Consumer Field for Game Consoles?
For PC operating systems with existing applications (many of them proprietary), compatibility must be maintained in subsequent generations of CPUs.
When the first PowerPC was built (1993), most software was proprietary and most of applications were written for x86 or Motorola 68k CPUs.
Thanks to Free Software, it is now possible to run the same programs and OS recompiled for PowerPC, so we are no longer forced anymore to use an old CPU architecture.
Game consoles have a minimal operating system with a few small embedded applications. Games are typically written from scratch or are developed on cross-architecture engines. Thus they are less affected by a CPU change.