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Long marathon to see u-boot start on the Powerboard Tyche

Posted on by Communications Team

Last November quite some work went into trying to boot up the Powerboard Tyche prototype. In particular, Max Tretene from ACube Systems worked on:

  • the calculation of a newer RCW, the Reset Configuration Word
  • trying to program eeprom over I2C
  • trying to boot U-Boot from the SD
  • debug our Powerboard Tyche using an Oscilloscope according to indication of the motherboard designer

Programming the eeprom over I2C

Programming the eeprom over I2C is not possible with our USB programmer because the power supplied to the chip also powers other components on the notebook board. Since the power consumption is high, the USB port goes into protection, and even if we supply power to the notebook board at the same time, the programmer does not work.
We have tried by not feeding it from the programmer but by powering the board and carrying only the I2C and MASS signals, but without success.

For the I2C eeprom we have used ground and I2C signals, powering the board, but the programmer again fails to program it as it reports an error IC not responding (chip not responding). If we use only the I2C signals without ground, with the board powered, then it sees the chip, but seems to write blank as it then only reads all zeroes values when checked.

After all these unsuccessful attempts, the motherboard is now in the hands of the electronic designer that will try to solve these problems.

Output from the serial port

Running programs from the SRAM. When downloading a test program to the SRAM and after setting the corresponding switches to RCW hardcoded, the program runs, but the output from the serial port is illegible. This is a problem of the prototype because repeating the procedure on the NXP T2080RDB DevKit the output from the serial ports reads “Core0-Thread0: Welcome to CodeWarrior!”. However, when we run the same program from the SRAM, but we deviate the output to the debugger console, the messages correctly shows up.

Even if we checked many aspects to search where the problem lies, we could not find anything wrong. The cable we are using is working correctly on the NXP T2080RDB devkit, and checking the electronic design in the prototype does not reveal errors, it is quite similar to the corresponding design as in the original NXP T280RDB DevKit schematics, even the connector is the same.

The picture below show a debugging session on the SRAM. At the bottom right of the debugger console, you can see the correct message output, but that is not the case on the serial port.

sram debug sram output on console

Tests on the NAND programming were successful. We dumped the memory to a file and then we verified that U-Boot was flashed correctly. However, when selecting the switches to boot from NAND, the prototype board does not seem to do any booting. In fact, the ASLEEP signal LED stays ON, and from the power supply bank, it seems that the CPU is asleep.

The DDR cannot be initialised in any way. We do not have any further information about this initialisation at the moment because only very few simple SRAM tests can be run on the board.

The output on the serial, but the text is illegible, on devkit the output is readable and is this:
Core0-Thread0: Welcome to CodeWarrior!

Debugging the Powerboard Tyche to find out why it does not boot

The Sys_Clock have the same clock of the NXP T2080RDB DevKit.

One test was to check if the serial port have the correct baud rate.

The oscilloscope, the Powerboard Tyche and the Jtag debugger.
Powerboard Tyche serial output on the Oscilloscope.

It looks like that the serial output frequency is not not correctly set. We expect 115200 baud/s whereas from that looks a square half-wave gives approximately 32 Khz.

A second NXP T2080RDB Devkit for developing U-Boot

The U-Boot development process is being carried out by Bas Vermeulen, a Dutch developer working with us. As Bas dos not have an hardware based on the NXP T2080 CPU, he is forced to check any change applied to U-Boot indirectly by sending each newly compiled version to Max Tretene that have our Devkit. As you may have guessed, this process is quite slow and complicated. Fortunately, a dedicated hardware supporting the goal was found thank to the NXP support, and we will be able to provide Bas an additional T2080RDB DevKit next January 2024.

Changes to the PCB design and 3D scanning of the Notebook Chassis

Once we will be able to finally solve the problems preventing the booting of the Powerboard Tyche, we have to update the PCB layout to better fit into the Eclipse notebook chassis. To achieve this goal we plan to perform a 3D scans of the entire chassis so we can rearrange the PCB design according to the 3D model of the Eclipse Notebook Chassis. A preliminary and informal quote revealed that such a 3D scan could cost around 700 euro.

We finally thanks again for your support and donations that allow us to finance all these activities, greatly facilitating reaching our goal in a reasonable amount of time: a very good quality PowerPC based notebook release as open hardware.

Our speeches in Free Software events – October-November 2023

Power Progress Community Foundation’s lecture speech at The South Tyrol Free Software Conference, SFSCON  11th November 2023

Roberto Innocenti – Power Progress Community President + Powerboard Tyche prototype and Chassis
NXP Tech Days 24.10.23 From the left: Powerboard Tyche designer, PPC president and ACube Systems owner
Linux Day Milano 28.10.2023 Power Progress Community updates regarding Powerboard Tyche

fine tuning firmware for u-boot and develop Radeon driver for latest u-boot version

Posted on by Communications Team

It’s a quite some time has passed since the beginning of July when we posted about the start-up ramp that carefully calibrated, programming a complex integrated circuit with some logic (i.e. ramps, voltage thresholds, internal ways of making the PWM regulator work, and so on) and when the Complex Programmable Logic Device (CPLD) (Lattice LCMXO640C-3TN100C FPGA) was programmed for the very first time in order to manage all external peripherals connected to it.

In July we figured out  that a Jtag Debugger was very needed to debug our Powerboard Tyche, the only way to solve the causes of not seeing any U-Boot output. We were able to buy such a debugger thanks to the donations we are collecting with the  current campaign, we thank all donors for their support. 

The debugger is  the NXP CWH-CTP-BASE-HE Jtag Debugger + NXP CWH-CTP-COP-YE “Probe Tip, Removable, For Power Architecture Processors, JTAG to CodeWarrior TAP Base Unit” and, together with one of the three prototypes, we shipped it in August to Max Tretene that kindly accepted to be directly involved in the debug process of the motherboard. Soon, the task proved to be quite challenging, so after an internal discussion, we decided to  offer Max a reimbursement for all the time he was spending on the job, a reimbursement that was made possible to the donations we are receiving with the current campaign.

Dealing with hardware debugging is quite a hard and tedious job, and it was not easy to see something useful on the Jtag Debugger connected to the prototype motherboard. An additional adapter was required to attach the debugger because of the difference in the pin dimensions (2 vs 2.5). Max found it quite useful using the jtag debugger with our NXP T2080-RDB Devkit that was also shipped to him, because it allowed to test the procedure on a working platform and helped understanding the right configurations of the switches to boot up the board.

The two switches on Powerboard Tyche, other related info on Page 5 of our schematics

As our PowerBoard Tyche have not the third switch like the NXP T2080-RDB Devkit a few additional resistors were required to setup correctly the board to be able to switch on the Code Warrior debug connected to our Powerboard Tyche. Not just that, an additional update to the CPLD chip was required to setup the debugging system correctly. Finally, on the 16 of October, Max was able to see some sign of life from the NXP T2080 CPU on SRAM and on NAND Memory, as you can see in the screenshots below. These days we are working on NOR programming, waiting in the meantime for a CPLD update from the hardware designer. The NOR programming is needed to have access to the DDR and then start U-Boot.

SRAM programming – CodeWarrior® Development Suites for Networked Applications attached to Powerboard Tyche
NAND Programming – CodeWarrior® Development Suites for Networked Applications attached to Powerboard Tyche

Some possible changes to the hardware design

All these hardware tests were useful for planning some changes to the hardware design: few missing resistors for enabling the u-boot switches must be added and we need to move one chip because it does not fit quite right in the eclipse chassis.

The recent worldwide electronic components shortages we faced when making  the prototype Powerboard Tyche boards caused an unexpected -and incredible-  increase of the prices. More recently chip prices seem to be coming back to more reasonable prices, with the exception of the Marvell Sata3 controller.

As a consequence, we are evaluating the removal of the Marvell Sata3 controller to both free very-much needed space space and save some costs because at the moment such a chip costs around 90 euros per piece, quite a lot.

In fact, nowadays most SSD are available at a very good price with the M.2 form factor, so a Sata3 connection is not that essential anymore. People in a desperate need for a Sata connection could use the two Sata2 controllers inside the T2080 CPU.

Below we list the availability and prices of 

  • Marvell Sata 3 controller 88SE9235A1-NAA2C000, in 2022 we had payed around 130 euro per piece + VAT, 1 per PCB, total 3 pieces. NOW Win Source  In Stock, 3450 pieces 87 euro
  • TPS544B20RVFT 4.5-V to 18-V, 20-A synchronous SWIFT buck converter with PMBus programmability and monitoring in 2022 we had payed around 550 euro per piece + VAT, 1 per PCB, total 3 pieces NOW: TI Website: 2000 pieces around $8 per piece
  • 6-port, 12-lane, PCIe 2.0 Packet Switch PI7C9X2G612GP – Diodes in 2022 we had payed it around 250 euro per piece + VAT, 1 per PCB, total 3 pieces NOW Digikey 121 pieces 25 euro per piece
  • Surge Suppressors 100V OV, UV, OC and Reverse Supply Protection Controller with -50mV Reverse Threshold LTC4368IDD-1#PBF in 2022 we had payed it  around 100 euro per piece + VAT, 1 per PCB, total 3 pieces NOW Mouser 2.191  Unit Price around 4-5 Euro

Compile and test of an updated version of U-Boot

We hired Bas Vermeulen to obtain a running version of the most recent version of U-Boot on both the NXP T2080-RDB Devkit and on the Powerboard Tyche prototype. In addition, we asked him to develop an AMD/ATI Radeon driver for U-Boot, a work that he carried out last August. The results of his effort is publicly available on our GitLab U-Boot repository.

Unfortunately, until our Powerboard Tyche will not be able to reach  the U-Boot startup process, Bas will be limited in developing and testing U-Boot on the NXP T2080-RDB Devkit. For that reason, Max Tretene is actively supporting Bas in testing the U-Boot binaries generated by Bas on the Devkit.

As you can see on our U-Boot gitlab repository, Bas was hard at work compiling very recent versions of U-Boot during last August. Unfortunately,  because of causes of force majeure, Bas was unable to continue working during September, but he should be back on track the very next days.

Below a short list of the main issues Bas is working on:

We finally thanks again for your support and donations that allow us to finance all these activities, greatly facilitating reaching our goal in a reasonable amount of time: a very good quality PowerPC based notebook release as open hardware.

We still do not have yet a formal quotation of the design of the heat pipes for cooling down both the CPU and the MXM video card. Informally, we estimated approximately 10000 euros. At the moment we are very much focused in making the Powerboard Tyche prototypes working, at least up to the point of being able to launch U-Boot.

CE mark certification financed! New campaign for the software part and heat pipes

Posted on by Communications Team

Once again we want to thank you all for the great support and great enthusiasm you demonstrated during the CE mark donation campaign. We ended the campaign with a total amount of 12500€ (https://en.wikipedia.org/wiki/CE_marking), this is a huge milestone for us all and we are so very grateful.

By financing the CE mark certification you have shown us that you believe in the project and our vision of creating a fully open hardware notebook motherboard based on the alternative PowerPC CPU architecture.

We closed the campaign with around € 4000 more than expected, and this extra money will cover some of the extra and unplanned costs we faced for the increased price of electronic components and the extra costs of the three MXM video cards (360 USD each).

The CE mark certification is a mandatory requirement for selling electronic products in the European Union. It ensures that our notebook motherboard meets the safety, health and environmental standards of the EU. Without it, ACube Systems would not be able to launch and sell our Notebook on the EU market. Getting the CE mark certification is not an easy nor a cheap process as it involves rigorous testing, documentation and quality controls.

Legacy Slimbook Eclipse cooling metal pipes to be redesigned

However, the CE certification process can be performed only when the product can be considered completely finished, and that means once the board works, the cooling metal pipes are in place and all is assembled into the selected slimbook eclipse chassis.

Current activities

The Tyche Motherboard has surpassed all the electrical checks, and now the the key activities being performed concentrate on the hardware initialization procedures.

The start-up ramp was carefully calibrated, programming a complex integrated circuit with some logic (i.e. ramps, voltage thresholds, internal ways of making the PWM regulator work, and so on).

The Complex Programmable Logic Device (CPLD) is a Lattice LCMXO640C-3TN100C FPGA is programmed to manage all external peripherals connected to it (see the block diagram and wiring diagram on page 15), manage the interrupts, data, boot reads, set resources according to the CPU and is able to reset all peripherals.

our Tyche motherboard under testing

Working on U-Boot

Currently, a small team of volunteers are working on U-Boot . We are decided to buy a JTAG debugger, a quite useful tool indeed that will make the hardware debugging much easier.

We learnt how to configure and build U-Boot, and we set up a cross-development PowerPC toolchain and the related Device Tree Blob that is used to describe the physical configuration of each hardware component available on the motherboard. You may keep an eye on our attempts by looking at our GitLab pages. We started by re-compiling our old U-Boot binary dating back to 2019, the one that we are currently using on our NXP T2080RDB devkit and also trying to compile a newer U-Boot version from a the DENX mainline vanilla branch without our patches. We are now kindly assisted by Max Tretene, the same guy working at ACube Systems that compiles U-Boot for their motherboards such as the Sam440 or the Sam460ex. Max is currently available to introduce hardware support to AMD/ATI Radeon graphics cards in U-Boot, (ndr.: he recently told us that his spare times is not enough so we are proposing him to work under payment) stay tuned for more in-depth posts about it. In the hope of speeding up the development, we provided Max Tretene with our NXP T2080RDB devkit in early June.

We want to thank the dedicated small group of volunteers and especially Max Tretene for their precious spare time spent in trying to configure and compile U-Boot, we very much appreciate their availability and effort, even if a successful result is yet to comes. In addition, we greatly appreciated the offer made by a professional engineer – not to be disclosed yet- that is ready to work for us on U-Boot for a very reasonable amount of money.

Launch of a new fundraising campaign

After quite some internal discussion, we finally decided to launch a new fundraising campaign aimed at support and speeding up multiple actions:

  1. Buy a JTAG Debugger
  2. Design of the heat pipes for cooling down both the CPU and the video card;
  3. Prototype of a heat pipe fitting our Slimbook chassis, a requirement to proceed to the CE certification process;
  4. Development of an AMD/ATI Radeon driver for U-Boot;
  5. Development of the device thee to fully exploit each hardware component of the board;
  6. Compile a custom  U-Boot binary from up-to-date DENX sources;
  7. Provide the entire toolchain for cross compiling U-Boot and the device tree for PowerPC;
  8. Provide the documentation detailing all the technical aspects of both U-Boot and the device tree so that anybody will be able to understand how to rebuild it from scratch and how to customize it.

In carrying out these actions, we will try our best to optimize both the support of the involved volunteers (any additional help is more than welcome!) and the contracted software engineer(s).

At the moment we only have a rough idea of the amount of required hours of paid work required to complete U-Boot and its closely related device tree. After some internal investigation, a reasonable rough estimate could be at least 100 hours, but it may take more to reach the goal.

We do not have yet a formal quotation of the design of the heat pipes for cooling down both the CPU and the MXM video card. During an informal discussion with electronic engineers that have experience in the design and production of these heat pipes, we estimated approximately 10000 euros.

To sum up, the title of next campaign is “Development of software components and heat pipes for the Powerboard Tyche” and its breakdown costs are the following:

  • Around 100 hours of work of a software engineer(s) for the customized U-Boot, the device tree and the AMD/ATI Radeon video driver: 5000 euros
  • JTAG debugger 1000 euro
  • design of the heat pipes and production of 3 of them for the three prototypes: 10000 euro

The estimated amount to collect with the next campaign is 16000 euros.

We really hope that you will assist us once again during this final journey. We are that close to making it happen: a 64 bit, multi core, PowerPC based notebook fully open hardware with up to today’s standards devices and interfaces!

Prototypes testing results

Posted on by Communications Team
Picture by PublicDomainPictures from Pixabay

The laptop prototypes testing is progressing great. We tested the primary power supply stage of the CPU, one the most power hungry components in the board, and it is being fine-tuned thanks to a programming apparatus. The chip in charge to power up the CPU NXP T2080 is the Texas Instruments TPS544B20RVFT (Switching Voltage Regulators 4.5-18V 20A SWIFT) as explained at page 37 in our electrical schematics.

The start-up ramp needs to be carefully calibrated, a complex integrated circuit with a some logic that needs to be programmed to make it work properly (i.e. ramps, voltage thresholds, internal ways of making the PWM regulator work, and so on).

The other power supplies are a half a dozen voltage regulators and are meant to power elements such as the PCIe, the RAM, the internal peripheral buses, the connected devices, the Non-Volatile Memory Express (NVMe) and the clock generators the are essential to make the board work properly. The Eclipse Legacy Battery was tested and is recharging properly.

The Complex Programmable Logic Device (CPLD) is a Lattice LCMXO640C-3TN100C FPGA and has to be programmed to manage all those external peripherals connected to it (see the block diagram and wiring diagram on page 15 ), manage interrupts, data, boot reads, set resources according to the CPU and reset all peripherals.

Powerboard Tyche, top side. The visible biggest gray chip is the CPU NXP T2080 Power Architecture CPU.

So far so good, the electronic design seems to work correctly, at the moment we are only fine-tuning each electronic component. If all checks continues like this, we might end all electronic debugging in the next few weeks and we can consider this very delicate phase successfully completed. After that, we plan to place the first code in the CPLD, and right after that we should be ready to load U-Boot, the first-stage and second-stage bootloader. We are trying to re-patch a recent version of U-Boot, quite some time has passed since we patched it to make it recognizing the graphic board we mounted on the PCIe port on the NXP T2080RDB board. Not just that, we must carefully customize the device tree to correctly map all peripherals available on the motherboard.

If for it concern the electronical components we can safely rely on the (paid) support of an expert engineer, for setting up U-Boot it’s up to us to make it work properly, and more importantly, to make it correctly recognize all peripherals, especially the SD card, the FLASH and, even more importantly, the two DDR3L RAM slots.

We would like to thank everyone for the continuous flow of donations, and please, continue to do so.

At the moment we still need funding to cover the extra costs we faced for the simply crazy prices we paid for the electronical components mounted on the prototypes motherboards and especially for getting our hands on two MXM graphic boards based on AMD chips.

For two MXM AMD E9174 video cards with 4GB RAM we have spent 780 dollars ( 360 each) and 185 euro of import Tax around 965 euro .Considering all chips, the cost of each prototype resulted 1200 euros higher than what was initially planned 4392 euros more (1200 x 3 + 22% VAT). So we need to collect around 5357 euro more than the goal of the last donation campaign.

Donations and professional for u-boot

In addition, after an initial round of experiments, we are still struggling to successfully customize U-Boot and to properly setup the device tree. Most of us already spent quite some time on the task during our spare time (remember, we are all volunteers with a proper day job and a personal life ;), so we are seriously evaluating to assign the job to a professional to get the job done in a reasonable amount of time, and to do that we need your financial support!

Prototypes ready, let’s proceed to test them.

Posted on by Communications Team

Finally, the three prototypes are ready as you can clearly see from the pictures below.

The resulting cost of each prototype resulted in 1200 euros (without VAT) higher than what was initially planned due to the global shortages of electronic components that have skyrocketed prices of some important chips. So, more donations are needed to fund these 4392 euros more (1200 x 3 + 22% VAT).

Powerboard Tyche, bottom side.
Powerboard Tyche, top side. The visible biggest gray chip is the CPU NXP T2080 Power Architecture CPU.

Now the Hardware Tests stage has started, but prior to that we still need to solder the HDMI connector that has arrived too late to be included during the production phase.

Soon, our Open Hardware motherboard called “Powerboard Tyche” will be inserted in its notebook body chassis for starting the multiple hardware tests.
Below, you can see a picture of the old dummy PCB used for testing how to fit in the notebook.

Slimbook Eclipse Notebook
The external view of the Notebook body

The notebook specifications are the following:

  • CHASSIS: Slimbook Eclipse notebook case 15,6”
  • CPU: NXP T2080, e6500 64-bit Power Architecture with Altivec technology
    • 4 x e6500 dual-threaded cores, low-latency backside 2MB L2 cache, 16GFLOPS x core
  • RAM: 2 x DDR3L SO-DIMM slots
  • VIDEO: MXM3 Radeon HD Video Card (removable)
  • AUDIO: C-Media 8828 sound chip, audio IN and audio OUT jacks
  • USB: 3.0 and 2.0 ports
  • STORAGE:
  • NETWORK:
    • 1 x Gigabit ethernet RJ-45 connector
    • WiFi connectivity
    • Bluetooth connectivity
  • POWER: on-board battery charger and power-management

Powerboard Tyche PCB source

This work was made using Mentor Expedition and it is ready and uploaded into our repository with all reported issues fixed, including issue number 5, the last one corrected . Thanks to our collaborators we are able to export this work using Altium form so the next days we will publish it and we will try to convert it to Open Source Kicad format ( and probably loosing something in the conversion process) . In our older post we have give more details regarding the PCB sources.