3d scanner Archives - GNU/Linux Open Hardware PowerPC notebook

Last November quite some work went into trying to boot up the Powerboard Tyche prototype. In particular, Max Tretene from ACube Systems worked on:

the calculation of a newer RCW, the Reset Configuration Word
trying to program eeprom over I2C
trying to boot U-Boot from the SD
debug our Powerboard Tyche using an Oscilloscope according to indication of the motherboard designer

Programming the eeprom over I2C

Programming the eeprom over I2C is not possible with our USB programmer because the power supplied to the chip also powers other components on the notebook board. Since the power consumption is high, the USB port goes into protection, and even if we supply power to the notebook board at the same time, the programmer does not work.
We have tried by not feeding it from the programmer but by powering the board and carrying only the I2C and MASS signals, but without success.

For the I2C eeprom we have used ground and I2C signals, powering the board, but the programmer again fails to program it as it reports an error IC not responding (chip not responding). If we use only the I2C signals without ground, with the board powered, then it sees the chip, but seems to write blank as it then only reads all zeroes values when checked.

After all these unsuccessful attempts, the motherboard is now in the hands of the electronic designer that will try to solve these problems.

Output from the serial port

Running programs from the SRAM. When downloading a test program to the SRAM and after setting the corresponding switches to RCW hardcoded, the program runs, but the output from the serial port is illegible. This is a problem of the prototype because repeating the procedure on the NXP T2080RDB DevKit the output from the serial ports reads “Core0-Thread0: Welcome to CodeWarrior!”. However, when we run the same program from the SRAM, but we deviate the output to the debugger console, the messages correctly shows up.

Even if we checked many aspects to search where the problem lies, we could not find anything wrong. The cable we are using is working correctly on the NXP T2080RDB devkit, and checking the electronic design in the prototype does not reveal errors, it is quite similar to the corresponding design as in the original NXP T280RDB DevKit schematics, even the connector is the same.

The picture below show a debugging session on the SRAM. At the bottom right of the debugger console, you can see the correct message output, but that is not the case on the serial port.

Tests on the NAND programming were successful. We dumped the memory to a file and then we verified that U-Boot was flashed correctly. However, when selecting the switches to boot from NAND, the prototype board does not seem to do any booting. In fact, the ASLEEP signal LED stays ON, and from the power supply bank, it seems that the CPU is asleep.

The DDR cannot be initialised in any way. We do not have any further information about this initialisation at the moment because only very few simple SRAM tests can be run on the board.

The output on the serial, but the text is illegible, on devkit the output is readable and is this:
Core0-Thread0: Welcome to CodeWarrior!

Debugging the Powerboard Tyche to find out why it does not boot

The Sys_Clock have the same clock of the NXP T2080RDB DevKit.

One test was to check if the serial port have the correct baud rate.

The oscilloscope, the Powerboard Tyche and the Jtag debugger.

Powerboard Tyche serial output on the Oscilloscope.

It looks like that the serial output frequency is not not correctly set. We expect 115200 baud/s whereas from that looks a square half-wave gives approximately 32 Khz.

A second NXP T2080RDB Devkit for developing U-Boot

The U-Boot development process is being carried out by Bas Vermeulen, a Dutch developer working with us. As Bas dos not have an hardware based on the NXP T2080 CPU, he is forced to check any change applied to U-Boot indirectly by sending each newly compiled version to Max Tretene that have our Devkit. As you may have guessed, this process is quite slow and complicated. Fortunately, a dedicated hardware supporting the goal was found thank to the NXP support, and we will be able to provide Bas an additional T2080RDB DevKit next January 2024.

Changes to the PCB design and 3D scanning of the Notebook Chassis

Once we will be able to finally solve the problems preventing the booting of the Powerboard Tyche, we have to update the PCB layout to better fit into the Eclipse notebook chassis. To achieve this goal we plan to perform a 3D scans of the entire chassis so we can rearrange the PCB design according to the 3D model of the Eclipse Notebook Chassis. A preliminary and informal quote revealed that such a 3D scan could cost around 700 euro.

We finally thanks again for your support and donations that allow us to finance all these activities, greatly facilitating reaching our goal in a reasonable amount of time: a very good quality PowerPC based notebook release as open hardware.