We now have the complete electronic source design for our new desktop design in our hands!
This week, ACube Systems and some volunteers from our association will review the design. We expect the manufacturer to start setting up the PCB layout for the new Powerboard Tyche Desktop on October 20th. This is part of our strategy to focus on creating a stable, functional desktop version of the core computing platform by the end of 2025.
The PCB design phase (Phase 2) will begin shortly after the schematics and Bill of Materials (BOM) are sent to the manufacturer. We anticipate that this step will allow the manufacturer to provide us with an estimate of the cost and timeline for the PCB layout design. This cost and timing estimate will then be shared with the community “just in time.”
Technical Components and NXP Review
We have verified that the availability of SATA2/3 controllers is poor, and the chip Lattice Silicon Image SiI3132 chip that we selected is no exception. We decided to include it in our desktop board to ensure backward compatibility with SATA devices, such as DVD and HDD.
We do not use the on-chip T2080 SATA2 controller because we prefer to use the T2080’s three x4 PCIe Gen3 configuration to optimize the speed of video cards and storage controllers. This configuration cannot coexist with the on-chip SATA2. In any case, the best performance is possible thanks to our M2 motherboard interfaces.
In our board design, we have an SPI connection for an external LCD, which can be used as a secondary screen or for debugging and diagnostics. It is also useful when setting up u-boot and when no video card is connected to the board.
Our board design includes GPIO connectors that can be used to connect other devices that don’t use USB, SPI, or PCIe buses.
Our desktop design is derived from our old notebook design and the original NXP T2080 RDB (Release F) design. We are integrating many components specified in the reference board, including critical monitoring hardware.
This includes the OnSemi ADT7481ARMZ thermal monitor, which has been upgraded to the OnSemi NCT72. The ADT7481 is used as the thermal monitor or temperature sensor on the original NXP T2080 reference design board. On that board, the ADT7481 (designated U34) is usually connected via the I2C_1 bus with the address 0x40. The T2080 processor itself contains a temperature diode designed to be used with system temperature monitoring devices, such as the Analog Devices ADT7461A. This similar part is mentioned in the documentation for the T1042 chip, which highlights the standard use of such monitoring.
Designers have changed other components from the original T2080 RDB design and our notebook design due to the availability of new compatible models, such as the N25Q512A13 FLASH SPI, which is substituted for the EvKit Micron MT25QL512A due to its limited availability.
Due to the changes in components, we will need to modify the VHDL code of the CPLD chip when we have the prototypes in our hands. Therefore, we must take into account the additional cost of this task.
To ensure full compliance and open-source publication readiness,
The designer will fill out the NXP review questionnaire [draft post 2025-10-12] simultaneously.
The questionnaire and the Cadence schematic source will then be sent to NXP.
The main goal is to receive a full or partial agreement to publish the parts of our design derived from the original NXP T2080 RDB (Release F) as open hardware.
We anticipate a robust boot-up because the components and firmware are similar to those of the stable T2080 RDB. The specific CPLD is programmed using the original CPLD source code of the T2080 RDB. Once NXP grants the necessary agreement, we plan to publish the source schematics and evaluate the use of a recent CERN Open Hardware License version.
Upcoming Project Phases
The next anticipated milestones, pending finalization of cost estimation:
Phase 2: PCB design. (tentatively scheduled two months after the completion of the schematics).
Phase 3: Prototype production (tentatively scheduled one month after PCB design).
Phase 4: Prototype testing (tentatively scheduled one month after prototype production).
We continue to rely on the community’s support. Recurring donations are dedicated to the campaign aimed at recovering costs already incurred for notebook testing and CPLD firmware fixing.
We are searching volunteers to test Debian PPC64 and fix packages
Finally, we need more volunteers to support the necessary software efforts, including Debian PPC64 testing, as we cannot ask for additional donations for this purpose.
Below is an updated list of specs for the desktop board being designed.
Form Facttor: Micro ATX
CPU: NXP T2080, e6500 64-bit Power Architecture with Altivec technology
4 x e6500 dual-threaded cores, low-latency backside 2MB L2 cache, 16GFLOPS x core
RAM: 2 x DDR3 Slots
VIDEO
PCIE3 x16 VIDEO Card 1
PCIE2 x16 VIDEO Card 2
AUDIO: C-Media 8828 sound chip, audio IN and audio OUT jacks (3x2)
USB: 2 USB 3.0 ports
2 USB 2.0 ports
2 USB 3.0 ports internal for FRONT
STORAGE:
2 NVM Express (NVMe)
2 x SATA2
1 x SDHC card reader
NETWORK:
2 x Gigabit ethernet RJ-45 connector
We really appreciate your patience! Despite the silence on our end, we’ve seen that our incredible community – both old friends and new supporters – have continued to donate continuously. An infinite thanks to all of you, our amazing current, past, and future donors! Your unwavering support truly fuels our efforts and keeps the dream alive.
As we shared in our last post, the work with the previous designer hit a significant hurdle: we just couldn’t get the board to reach the crucial boot stage.
This led us on a search for a new designer, someone with specific skills and experience with PowerPC architecture. We were really pleased to find a talented new designer who was available from the beginning of 2025, who can even rely on an additional person who is an expert in firmware programming. Following our plan, we used January and February to make the big move, getting all the equipment transferred over to this new designer’s team.
We held off on publishing updates because, honestly, we were waiting for that breakthrough moment – the good news we could finally share with all of you. As things were showing quite promising (e.g. improved CPU signals outputs), we had high hopes that this new collaboration would quickly move us past the booting issues. In parallel, we also tried improving U-Boot and led an additional T2080RDB, the development board that was kindly provided by NXP, to one of our collaborators, but due to personal health problems, he can no longer contribute to the project.
Our work with the new designer has been focused on rigorous testing. On April 9th, we saw that the board’s behavior was frustratingly similar to the devkit – it still wasn’t booting. This prompted a dedicated session on April 14th for one last intensive attempt to find the root cause. As part of this deep dive, we de-soldered the Marvell chip, which is the SATA3 controller.
Marvell 88SE9235A1-NAA2C000 Sata 3 chip removal to test Powerboard Tyche
Removing this component was actually something we had already planned to do for the upcoming prototype version as we streamline the design. To help isolate the issue even further, we also de-soldered the Pericom chip.
The overall outcome? Despite taking these significant steps, the board still did not boot. It exhibited exactly the same behavior. We were, frankly, quite upset and left without words.
It’s incredibly challenging when you put in the effort, try to simplify things, and the core problem persists. So far, we have spent around 6000 Euros with the newly hired hardware designer, and even if things have improved, showing the expected NXP documented behaviors of the NXP reference development board, after two years with the prototype motherboards in our hands, we still are not able to boot it.
The hardware designer who created our Powerboard Tyche worked between April and July on one of the three prototypes, focusing on fixing the board firmware. These fixes required a series of checks to determine if any additional adjustments were needed for the board itself, and a complete analysis of electronic signals was performed. This analysis was provided later in September. The same fixes were applied to the second prototype (we have three prototypes).
u-boot 2018.11 enabled AMD video cards
Additionally, Max Tretene from ACube Systems was hard at work on our NXP T2080-based DevKit and completed a newer version of U-Boot in May, which finally enabled graphical output on AMD Radeon video cards during booting. You can find the updated source code on our GitLab. Below you can see the new U-Boot in action booting up the NXP T2080-based DevKit.
Below is a photo showing the Powerboard Tyche during an electronic test session conducted last August.
In August, the hardware designer sent back two prototypes to our firmware engineer. ACube Systems purchased an oscilloscope to continue analyzing signals on the prototypes, since the oscilloscope previously used by the firmware engineer was on loan.
In September, signal analysis using the oscilloscopes began, comparing the NXP T2080-based DevKit and our Powerboard Tyche to identify differences. Many differences were found in the power-up sequences, so we asked the hardware designer to fix the CPLD program responsible for governing the signals.
Below is a picture of the expected power-up signals as explained in the T2080 Manual.
Below is picture showing the signals from the Powerboard Tyche last August, a picture extracted from the Test Report provided by the hardware designer.
As you can see above there is some difference of PORESET_B and HRESET_B between what was found during the hardware tests on pur board and what is expected in the NXP manuals.
In September, a new series of tests were performed. Below are two pictures from the oscilloscope showing the output of different attempts while reprogramming the CPLD of the Powerboard Tyche.
As we can see on the screenshot even the tension of 2,51 volt was wrong, as it should be not more than 2 volt.
During September and October, there were many reprogramming cycles of the CPLD. Each time, the hardware designer recompiled the HDL of our CPLD and sent it to our firmware engineer, who had two prototypes in hand. Reprogramming the prototypes was quite slow, as neither the hardware designer nor the firmware engineer were working full-time in our project. We sent one prototype back to the hardware designer, and by the end of October, he had completed the CPLD updates. At the end of this hard work the CPLD finally generates the expected power-up signals, reproducing the same signals generated during power-up of the NXP T2080-based DevKit.
The final version of the CPLD firmware (published on GitLab) modifies the behavior of the two signals PORESET (yellow) and HRESET. Indeed, the oscilloscope shows that the two signals now behave differently compared to previous versions.
By the end ofOctober, the signals on the Powerboard Tyche finally looked correct (picture below)
As you can see the now the tension is correct, around 1,95v, in August was 2,51v
Unfortunately, the changes to the CPLD did not resolve the boot-up process of the entire board.
Strangely enough, during tests we found differences in the power-up behavior between two of the prototype boards: one in the hands of the firmware engineer (FE) and the other in the hands of the hardware designer (HE). Here are the three differences we found:
On the HE board, the ASLEEP LED stays off if the SD card with U-Boot is inserted and lights up if it is not inserted.
On the FE board, the ASLEEP LED always stays on, regardless of whether an SD card is inserted or not.
On the HE board, the oscilloscope shows activity on the SD signals, while on the FE borrowed, there is no activity at all.
We are investigating the possible causes of this different behaviors, such as a potentially different patches. We have sent the third prototype, which was in the hands of Roberto Innocenti during the presentation in October-November 2023, back to the hardware designer to verify its behavior.
Differences were also found while performing the usual test with our JTAG debugger, where we encountered some unusual and strange characters in the output.
New Partners to reach the goal
Due to the significant latency and unreliability of the original hardware designer, we are now forced to find other partners to reach our goal of having the motherboard ready for production in 2025. We started the process of searching for a new company in August, and finally, in November, we found a new highly skilled Italian company for prototype production. This company has decades of experience and a new hardware designer with experience in PowerPC design, which is a great accomplishment for us since such expertise is becoming increasingly rare.
In the transition from one company to another, we are now facing some additional work because the current PCB design is based on Mentor Expedition software (a software now acquired by Siemens), while the new hardware designer uses the Orcad software. Fortunately, we have previously worked on such a task and have already attempted the conversion to Altium software. However, we will need to perform the conversion with greater care to ensure that all components are completely and correctly exported.
The past work on the mechanical aspects of the PCB to fit it into the Slimbook chassis was performed by a previous company that unfortunately generated some dimensioning errors in our existing prototypes therefore the new company has to fix also these problems.
Even if this new company was already known as it successfully worked with ACube System in the past, it was not previously selected for working on the laptop because of its somewhat higher cost. So at this point we are left with no choice but to entrust the job to them if we really want to find out what’s wrong with the board.
Required changes to the motherboard
We have already had the opportunity to explain the history of the board to the new company and to the new hardware designer and requested their investigation into the possible causes preventing the board from booting up. We agreed on a complete and in-depth analysis of the entire pre-boot process of the board. Based on their checks, we may need to implement further patches or introduce additional changes to the electronic design as a worst-case scenario.
The new hardware designer , obviously had other projects running before starting ours and will be able to start working on our board by January 2025.
In addition to potential electronic fixes, we have already planned some hardware changes as stated in a previous post (link). The goal is to make new prototypes with changes that will lower the overall cost and to do so, we will drop the SATA3 chipset, which is quite costly and considered obsolete due to the presence of three M.2 connectors. We will also drop the SIM card reader and one of the two EPROMs, as we only need one.
Due to the unknown amount of work required, the cost of the activities to be carried out by the new company cannot be estimated. On top of that we plan to make new, hopefully final, prototypes that should cost around 1500 euros each plus around 2000 euros for setting up the prototype production plant.
Campaign Change and Upgrade.
We particularly thank to all recurring donors that keep a constant contribution allowing us to keep the project ongoing.
We have updated the current donation campaign, postponing the heat pipe redesign for a later stage, and refocused on supporting the required work to make the Powerboard Tyche function correctly.
To reach the new goal, we need to pay a new hardware designer that will help us understand what is wrong with the current motherboard prototypes, potentially leading to a partial electronic redesign. We need to produce a new prototype with mechanical fixes, ensuring the correct placement of the board inside the chassis and some connector placement adjustments. Additionally, we plan to drop the SATA3 chipset, the SIM card reader, and the unnecessary additional EPROM.
In addition, we still have to pay the firmware engineer, who was fundamental in making progress in 2024. Without his strong work in fixing and comparing signals between the NXP T2080-based DevKit and our motherboard prototypes, and his continuous feedback to the hardware designer, the needed fixes on the CPLD (Lattice LCMXO640C-3TN100C FPGA) would not be possible.
93.00% Raised
€13,020.00 donated of €14,000.00 goal
63 Donors
3 Days Left
Call for a Scientific & Technical Committee
We are setting up in our not-for-profit association a Scientific & Technical Committee that, for example, will provide solutions for our Open Hardware project, examine other Open Hardware projects, adopt other OpenISA CPU, and develop additional Open Hardware Notebook design. Anyone of the associated member of the Power Progress Community will be able to join this committee.
By establishing this committee, we intend to make our association and our PPC Community a suitable place allowing the personal and social development, sharing the motto “Knowledge in solidarity and to be in service of liberation from conditions of constraint and oppression and for freedom of choice”.
Call for developers
We ask any capable developer to increase the number of software supporting PowerPC 64 bit platform (aka PPC64) as the target architecture. In particular, we welcome anyone willing to introduce support for the big-endian variant of the PPC64 architecture, the only one supported by the NXP T2080 CPU that we selected for out PowerPC notebook.
We are currently revising our GitLab based repositories that we setup during the last years while trying to add support to the PPC64 platform. We invite existing and new collaborators to identify potential libraries and GNU/Linux applications to which they are willing to work on, even adding support to a small piece of software may allow bigger application to start working on PPC64 architecture, do not underestimate what even a small contribution may achieve in a bigger picture.
More software working on PPC64, means a better chance for our Powerboard Tyche notebook to become a useful piece of hardware for a bigger number of people, making it an appealing alternative for a broader community.
In case you want to help out on any kind of software stack, please contact us or fill our collaboration survey. In case you are already a contributing volunteer to any existing open source software development, adding support for the big endian PPC64 platform is more than welcome.
If you do not have direct access to a physical PPC64 hardware platform, we can provide you access to our IBM Power9 based environment that is kindly provided by OSU Open Source Lab that we thanks so much for their support.
Finally, the three prototypes are ready as you can clearly see from the pictures below.
The resulting cost of each prototype resulted in 1200 euros (without VAT) higher than what was initially planned due to the global shortages of electronic components that have skyrocketed prices of some important chips. So, more donations are needed to fund these 4392euros more (1200 x 3 + 22% VAT).
Powerboard Tyche, bottom side.Powerboard Tyche, top side. The visible biggest gray chip is the CPU NXP T2080 Power Architecture CPU.
Now the Hardware Tests stage has started, but prior to that we still need to solder the HDMI connector that has arrived too late to be included during the production phase.
Soon, our Open Hardware motherboard called “Powerboard Tyche” will be inserted in its notebook body chassis for starting the multiple hardware tests. Below, you can see a picture of the old dummy PCB used for testing how to fit in the notebook.
POWER: on-board battery charger and power-management
Powerboard Tyche PCB source
This work was made using Mentor Expedition and it is ready and uploaded into our repository with all reported issues fixed, including issue number 5, the last one corrected . Thanks to our collaborators we are able to export this work using Altium form so the next days we will publish it and we will try to convert it to Open Source Kicad format ( and probably loosing something in the conversion process) . In our older post we have give more details regarding the PCB sources.
At the beginning of December 2021 we received an update about the required electronic components that are still missing. We have a total number of 22 missing components, and some of them are present on the board multiple times such as the MOSFET (see https://en.wikipedia.org/wiki/MOSFET).
Below a detailed list of the missing components in more pieces:
7 per pcb MOSFET – DMN3730U-7 N 750mA 30V POWER MOS – Diodes
9 per pcb Trans MOSFET – SI4925DY P-CH 30V 5.3A 8-Pin SOIC – ON SEMICONDUCTOR
4 per pcb Field Effect Transistor –NDC7002N MOSFET 2N-CH 50V 0.51A SSOT6 – ON SEMICONDUCTOR
3 per pcb IRLML6346TRPBF – N-Channel 30 V 3.4A (Ta) 1.3W (Ta) – Infineon Technologies
While ACube Systems is looking for 22 missing components contacting various distributors, we at the Power Progress Community, are trying to help searching these components. The main problem we are facing is not finding each component, the problem is the estimated delivery we are facing that most times is six month or more. For this reason we are evaluating to replace some of the components in order to get a more reasonable delivery time. In case you want to help out carrying out this task, you can the effort and conatct us.
QEMU at full speed with KVM on the NXP T2080 CPU
Thanks to Fabiano Rosas, Cédric Le Goater and Zoltan Balaton (see discussion at https://lists.gnu.org/archive/html/qemu-ppc/2021-12/msg00231.html) it is now possible to launch virtual machines at nearly native speed with QEMU on our NXP T2080RDB development kit, that mount exactly the same CPU as in our laptop.
KVM support for PowerPC Book3e e6500 CPUs will be first introduced starting with the linux kernel 5.16+ and with the next version of QEMU, most probably v7.0. If you want to try it now, you should get the release candidate of the kernel 5.16 and compile QEMU yourself from the GIT master branch
We successfully compiled the upcoming kernel and QEMU and then tested some virtual machines running Linux for PowerPC 64 bit in Big Endian mode. Below you can see a screenshot of QEMU running three virtual machines with KVM activated. The host system is our NXP T2080RDB devkit that runs Debian SID PPC64, then there is a VM with Debian SID PPC64 (bottom-right), then OpenSUSE Tumbleweed PPC64 (bottom-left), and finally VOID Linux PPC64 (top-right).
Please note that the KVM support to the e6500 PowerPC family is still in progress, so it may need some tweaking before it may be considered reliable.
Video of our last talks – October and November 2021
Open Power Summit 2021 NA
Prepare yourself to switch computing to Open Hardware Power Architecture
