This section is for people new to the PowerPC architecture (also called Power Architecture).
Though if you are an expert already you can enrich this page. Please send us information you want to be published here. Thank you.
The PowerPC architecture design is newer than the other successful CPU architectures:
X86 – year 1978
MIPS – year 1981
ARM – year 1983
PowerPC – year 1991
From the beginning PowerPC was designed with more features than other CPUs.
The Power Instruction Set Architecture is called Power ISA and is in continuous evolution.
Power Architecture (PowerPC) scales from embedded uses to Big Server Clusters.
Specs in short
- 64-bit architecture with a proper 32-bit subset
- Wide vector instructions with large register file allow efficient data moving without use of off-chip memory
- RISC architecture introduces Superscalar concept of multiple execution units: Branch, Fixed Integer, Floating Point
- AltiVec SIMD vector processing
- ISA 2.04/2.05/2.06 support multicore/multithreading, virtualization, hypervisor and Power Management
- Automotive space from Powertrain, Body and Chassis, to Safety and Infotainment.
- Compute – Volume server to the fastest and most resilient enterprise servers
- Consumer – core technology for the innovative game consoles (X-Box 360, Wii, PS3)
- High Performance Computing – Sequoia, the IBM BlueGene/Q system
- Wired Communications
- Wireless Communications
Altivec accelerator SIMD
- AltiVec technology is a vector or single instruction multiple data (SIMD) architecture that allows the simultaneous processing of multiple data for floating point and integer items in parallel.
- Developed 1996-1998 Standard from Power ISA 2.03
- consists of thirty-two, 128-bit architectural registers and 16 additional vector rename registers.
- The e6500 core includes a 16 GFLOPS AltiVec technology
Specs in deep (more info)
- fixed 32-bit wide instructions to ease their decoding
- load-store model, all operations are done within registers
- large number of registers (32 general purpose registers and 32 floating point registers)
- atomic (or exclusive) load-store instructions for use in a multicore context
- big endian order with the possibility to work in little endian
- 64-bit architecture with the behaviour of instructions specified for this mode
- no specific role for general purpose registers (r1 used as the stack pointer is an ABI choice, not an architecture one)
- MMU model not defined, it is implementation specific with globally 2 models for use in embedded devices or servers
Why PowerPC in the consumer field is adopted only for game consoles ?
CPU with many (proprietary) applications force to keep compatibility into next generation CPUs.
At the time the first PowerPC was built (1993) , all software was proprietary and all applications were written for x86 or Motorola 68k CPUs.
Thanks to Free Software now it’s possible to run the same programs and OS recompiled for PowerPC, so we are not forced anymore to use old CPU architecture.
Games console have a tiny OS with few embedded applications.
Games are written from scratch or are developed on cross-architecture engines. CPU change affects them less.